1. Field of the Invention
The present invention relates to semiconductor devices and particularly to a semiconductor device having an isolation oxide film near trenches provided in a semiconductor substrate and a method of manufacturing thereof.
2. Description of the Prior Art
Recently, semiconductor devices have been remarkably developed and various proposals have been made to accomplish a large scale integration in dynamic random access memories (DRAMs) without deteriorating the storage characteristics thereof.
FIG. 1 is a block diagram showing an example of a construction of a general DRAM. A memory cell array 101 comprises a plurality of word lines and a plurality of bit lines arranged to intersect with each other and memory cells are provided at respective intersections of those word lines and bit lines. A memory cell is selected for each intersection of one word line selected by an X address buffer decoder 102 and one bit line selected by a Y address buffer decoder 102. Data is written into the selected memory cell or the data stored in the memory cell is read out therefrom. An instruction for writing or reading of data is given by a read/write (R/W) control signal supplied to an R/W control circuit 104. In writing data, input data Din is applied to a selected memory cell through the R/W control circuit 104. On the other hand, in reading data, the data stored in the selected memory cell is detected and amplified by a sense amplifier 105 and the amplified output is provided to outside as output data Dout through a data output buffer 106.
FIG. 2 is an equivalent circuit diagram of a dynamic type memory cell shown for explanation of write/read operation of a memory cell.
Referring to FIG. 2, the dynamic type memory cell comprises a field effect transistor 108 and a capacitor 109. The gate electrode of the filed effect transistor 108 is connected to a word line 110 and the source/drain electrode thereof connected to the capacitor 109 is connected to a bit line 107. In writing data, the field effect transistor 108 is conducted by application of a predetermined charge to the word line 110 and accordingly a charge applied to the bit line 107 is stored in the capacitor 109. On the other hand, in reading data, the field effect transistor 110 is conducted by application of a predetermined charge to the word line 110 and accordingly the charge stored in the capacitor 109 is taken out through the bit line 107. Thus, a storage capacity of the memory cell is dependent on the capacity of the capacitor 109. Consequently, in order to increase an integration scale of a memory cell array, trench memory cells are developed in which trenches are formed on a semiconductor substrate and a charge storage region is formed on the inner surfaces of each trench, making it impossible to maintain or increase the storage capacities of the memory cells.
FIG. 3 is a plan view of a dynamic RAM hereinafter referred to as DRAM) of a folded bit line system using trench memory cells and FIG. 4 is a sectional view taken along the line IV--IV in FIG. 3. Those trench memory cells are disclosed for example in a lecture No. 9.6 of the International Electron Device Meeting of 1984 (IEDM '84).
Referring to FIGS. 3 and 4, a plurality of memory cells 12 are formed on a surface of a p type semiconductor substrate 1 and those memory cells 12 are isolated from each other by an isolation oxide film 8. Each memory cell 12 comprises a charge storage region 16 for storing a charge, a transfer gate 18, and an n type impurity region 20 connected to a bit line 22. The charge storage region 16 comprises a trench 5 formed in the main surface of the semiconductor substrate 1 (corresponding to a region surrounded by solid lines in FIG. 3), and an n.sup.+ impurity region 30 formed on a part of the main surface of the semiconductor substrate 1, including the inner walls of the trench 5, an oxide film 32 for capacitor covering the inner walls of the trench 5, and a cell plate 28 formed by polysilicon or the like to fill the trench 5 through the oxide film 32. The transfer gate region 18 comprises a channel region 34 between the impurity region 20 and the n.sup.+ impurity region 30, and a word line 26 formed by polysilicon or the like to be a gate electrode over the channel region 34. The impurity region 20, the transfer gate 18 and the n.sup.+ impurity region 30 constitute a switching transistor. Data write/read operation in FIG. 2 will be described referring to FIG. 4.
In data write operation, when a predetermined charge is applied to the word line 26, an inversion layer is formed in the channel region 34 and accordingly the impurity region 20 and the n.sup.+ impurity region 30 are conducted. Consequently, a charge applied to the bit line 22 is transferred to the charge storage region 16 through the invented channel region 34 and it is stored in the n.sup.+ impurity region 30. On the other hand, in data read operation, a predetermined charge is applied to the word line 26 to cause the charge stored in the n.sup.+ impurity 30 to pass through the inverted channel region 34 and to be taken out to outside through the impurity region 20 and the bit line 22.
The amount of the charge thus stored depends on an area of the n.sup.+ impurity 30 facing the trench 5, that is, the area of the inner walls of the trench 5 and accordingly formation of the trench 5 contributes to a large charge storage capacity compared with the plane area occupied by the charge storage region 16. More specifically, formation of the trench 5 and the trench capacitor utilizing the trench 5 makes it possible to ensure the capacitor having a relatively large capacity for charge storage with respect to a small area occupied by a fine memory cell.
In such a DRAM having trenches developed based on the above described background, an isolation oxide film 8 for isolation of adjacent cells is provided as shown in FIG. 4 so as to prevent mutual interference of the charges stored in the capacitors of the adjacent cells. Therefore, as the cells are made microscopic, a distance between the isolation oxide film 8 and the trench 5 concerned is unavoidably reduced.
FIGS. 5A to 5E are schematic sectional views showing steps of a conventional method of manufacturing an isolation oxide film formed near trenches.
In the following, this manufacturing method will be described referring to the figures.
First, an oxide film 111 is formed on a main surface of a semiconductor substrate 1 and an isolation oxide film 8 is formed by a well-known LOCOS method by using as a mask a nitride film 112 patterned in a predetermined form on the oxide film 111 (as shown in FIG. 5A).
Then, after the nitride film 112 and the oxide film 111 are removed, an oxide film 113 is formed on the main surface of the semiconductor substrate 1 and a nitride film 114 is further formed over the whole surface of the oxide film 113 as well as the isolation oxide film 8. An oxide film 115 to be used as a mask for etching trenches in the subsequent step is formed with a predetermined thickness on the nitride film 114 by a CVD method. Then, resist is formed on the oxide film 115 and a photolithographic process is applied thereto, whereby the resist 118 is patterned to have openings 117 corresponding to positions of trenches to be formed (as shown in FIG. 5B).
After the oxide film 115 is etched by using the resist 118 as a mask, the resist 118 is removed and the etching for forming trenches is applied to the semiconductor substrate 1 including the nitride film 114 and the oxide film 113 by using the etched oxide film 115 as a mask, whereby trenches 5 of a predetermined shape are formed (as shown in FIG. 5C).
Subsequently, wet etching is applied to remove the oxide film 115 used as the mask for the etching for formation of the trenches. On this occasion, the nitride film 114 is not etched; however, the oxide film 113 and the isolation oxide film 8 functioning as buffer materials between the nitride film 114 and the semiconductor substrate 1 are partially removed at the same time since those films face the inner walls of the trenches 5 (as shown in FIG. 5D).
Finally, after the nitride film 114 is removed and the remaining oxide film 113 is removed, another oxide film 116 is formed by the CVD method over the whole area of the main surface of the semiconductor substrate 1 including the inner walls of the trenches 5, whereby the isolation oxide film 8 for isolation of the adjacent elements between the trenches 5 is formed (as shown in FIG. 5E).
FIG. 6 is an enlarged sectional view showing the isolation oxide film 8 and the oxide film 116 around a trench 5 formed as shown in FIG. 5E.
In FIG. 6, an angle formed between a side surface of a trench 5 and the main surface of the semiconductor substrate 1 is acute on the side of the isolation oxide film 8 compared with the angle (about 90.degree.) on the opposite side. This tendency is particularly noticeable in the case where an end of the isolation oxide film 8 and the side surface of the trench 5 become close due to a microscopic size of each cell and a flat area of the main surface of the semiconductor substrate 1 does not exist in that portion, as is evident from FIG. 5C. In such a case, a thickness of the oxide film 116 in an edge portion "a" of the trench 5 on the side of the isolation oxide film 8 is very small. Since a dielectric strength of the oxide film 118 is defined by the film thickness in this portion, there are involved various disadvantages such as increase of initial failure or the like and lowering of reliability.
Since the film thickness of the oxide film 116 in this edge portion is particularly decreased by the CVD method, a method of forming an oxide film by sacrificial oxidation is often adopted to avoid such decreased.
According to this method, a thermal oxidation film including an edge portion of a trench is formed in an atmosphere at a high temperature of about 1050.degree. C. or more and that film is removed and thermal oxidation is further applied to form an oxide film with the edge portion being made round. However, if the film thickness of the oxide film at the edge portion becomes equal to that of the flat portion by using this method, the dielectric strength and the reliability of the oxide film are not improved so much compared with those in a flat structure. This is because a large residual stress caused by formation of the isolation oxide film 8 exist in a main surface portion (b) of the semiconductors substrate 1 between the edge portion (a) and the isolation oxide film 8, causing deterioration of adhesion with the oxide film 116.